1. Field of the Invention
The present invention relates to a transmitting apparatus, and it particularly relates to a transmitting apparatus which performs serial output.
2. Description of the Related Art
It is known that serial data communication is performed in order to reduce the number of signal lines in data communication between a plurality of electronic apparatuses (refer to Japanese Patent Laid-Open Nos. 2006-303915 and 2007-265261).
A transmitting-side apparatus disclosed in Japanese Patent Laid-Open No. 2006-303915 outputs a serial output synchronous clock acquired by multiplying a synchronous clock for data input by a phase locked loop (PLL) circuit. A parallel data signal input to a transmitting-side apparatus is converted to a serial data signal in synchronism with the serial output synchronous clock.
A receiving side apparatus converts the received serial data signal to a parallel data signal in synchronism with the serial output synchronous clock output from the transmitting-side apparatus.
The transmitting-side apparatus disclosed in Japanese Patent Laid-Open No. 2007-265261 converts a parallel data signal to a serial data signal in synchronism with the serial clock acquired by multiplying a reference clock. The transmitting-side apparatus outputs a transfer clock with an equal frequency to that of the reference clock.
A receiving side apparatus internally includes a PLL circuit and multiplies the received transfer clock to generate a serial clock and converts the serial data signal to a parallel data signal in synchronism with it.
In a transmitting-side apparatus of Japanese Patent Laid-Open No. 2006-303915, a serial output synchronous clock is output as a low voltage differential signal from an LVDS driver. On the other hand, a serial data signal is converted from a parallel data signal by a converting circuit which operates in synchronism with a serial output synchronous clock and is output as a low voltage differential signal from an LVDS driver. In other words, the serial data signal and the serial output synchronous clock have a difference in transition timing (skew) of the signals by the amount of delay due to the operation by the converting circuit. The skew varies in accordance with the operating condition such as the power supply voltage and temperature of the transmitting-side apparatus or the variation in apparatus characteristics due to a semiconductor process for producing the transmitting-side apparatus. Since a receiving side apparatus is required to accurately convert the serial data signal received from the transmitting-side apparatus to a parallel data even with the variations in delay time, the design of the apparatus may possibly be complicated.
Also in a transmitting-side apparatus disclosed in Japanese Patent Laid-Open No. 2007-265261, a transfer clock output from a PLL circuit is then output from a clock transmitting circuit. On the other hand, a serial data signal is converted from a parallel data signal by a converting circuit which operates in synchronism with a serial clock and is then output from a data transmitting circuit. Thus, Japanese Patent Laid-Open No. 2006-303915 may possibly have the same problem.